As semiconductor devices scale to smaller dimensions, the ability to harness device improvements with decreased size becomes more challenging. The synthesis of three-dimensional semiconductor transistors, such as fin type field effect transistors (finFET), or horizontal gate all around (HGAA) transistor devices involves challenging processing issues. HGAA structures are often referred to as a nanosheet device because the HGAA transistor formation entails formation of multilayers of nanometer-thick sheets of two different semiconductor materials grown in an epitaxial heterostructure, such as a stack of alternating silicon and silicon:germanium alloy (SiGe) layers, arranged in a vertical configuration. During one stage of formation, the nanosheet device is patterned into nanowire stacks, wherein the SiGe layers in the nanowire stack act as dummy wires, subsequently removed at later stages of processing to form free-standing silicon nanowires. The silicon nanowires can then be encased on four sides with gate material to form an HGAA structure. In known approaches, an epitaxial source drain is to be formed on the Si nanowires in a nanowire stack before the removal of SiGe dummy wires. This sequence entails protection of the SiGe dummy nanowires to ensure the epitaxial source/drain does not grow on the SiGe dummy nanowires, to facilitate removal of the SiGe dummy nanowires at a later stage. One unmet challenge for forming robust nanosheet devices is the ability to form insulating spacers in a controllable fashion, to passivate the SiGe layers in a nanowire stack, preventing epitaxial growth on the SiGe nanowires, while at the same time exposing the silicon nanowires for epitaxial growth thereon.
With respect to these and other considerations, the present disclosure is provided.